There are lots of things you need to know to write an emulator that aren't sufficient well explained in the User Guides and manuals. If you know the answer to any of these questions, please e-mail me
What are the initial states of the ACIA registers ?
That is, when the machine is powered up, before the CPU starts executing the OS. Presumably they have a fixed power-up state ?
When the 6850 ACIA does a master reset, are the parity error and framing error flags cleared ?
What's the initial configuration of the Analogue-to-Digital converter on power-up reset ?
That is, what channel does it start doing a conversion on, is it in ten- or eight-bit conversion mode, is the ADC busy and is a conversion marked as complete ?
What are the initial values of all the CRTC registers ?
Before the OS sets them all up correctly so that it's actually possible to see the display.
What's the initial power-up state of the 8271 FDC ?
What's the initial power-up state of the Econet controller ?
What's the initial power-up state of the serial ULA ?
Why does reading the write-only register in the serial ULA
turn off the cassette motor when it has been switched on using
*MOTOR 1 ?
What's the initial power-up state of the 6522 VIA ?
On the subject of the 6522 VIA, the manuals say that the T2 interrupt can only be re-enabled (after it has been triggered) by writing to T2CH or reading from T2CL. Is that because these actions also reset the interrupt flag or does this happen completely independently ?
And another... Read/Write of the ORA clears the interrupt flag in the IFR. Does Read/Write of the non-handshaking copy of ORA do the same thing ?
What is the power-up state of the Tube ULA registers ?
What is the power-up state of the Video ULA registers ?
What values are returned when the Video ULA registers are read ?
The Advanced User Guide says that the registers are write-only.
The System VIA writes some bits in a latch to determine the screen size for bitmap modes. How does the system know how big the screen is in Teletext mode ?
I have implemented many of the undocumented NMOS 6502 op-codes. There's no indication as to how they affect the SR flags in any of the documentation that I have. Can anyone tell me ?